Polycrystalline silicon (polysilicon) resistors are commonly used as load devices in a variety of digital and analog applications, and in particular, in Static Random Access Memories (SRAMs). SRAM cells with resistive loads are hereinafter referred to as the 4D/2R SRAM cells. Stacking polysilicon load resistors above the NFETs in 4D/2R SRAM cells is much appreciated in the design of the SRAM chip layout, because it results in a significant reduction in the SRAM cell size due to the fact that the cell area is only determined by the area used by the NFETs. It is now a general practice in the industry to have the load resistors of 4D/2R SRAM cells formed by resistive polysilicon lands obtained from a very thin layer of either intrinsic or lightly doped polysilicon material. However, because these load resistors must be fairly high-valued, i.e. in the tera-ohms (10.sup.12 .OMEGA.) range or above, limitations on the current drawn by the cell results in a limit of 1 megabit capacity of 4D/2R SRAM cell chips. As a matter of act, for increased capacities, the polysilicon layer must be so thin that the process tolerances are too difficult to control. In addition, 4D/2R SRAM cells are also very sensitive to soft errors produced by alpha particles. For memory larger than 1 megabit, stacked PFETs instead of polysilicon resistors have to be used as load devices, although this is at the cost of a significantly more complicated manufacturing process.
FIG. 1 shows a conventional 6D SRAM cell circuit, referenced 1, with PFETs as load devices. Two cross-coupled NFETs N1 and N2, referred to as the driver transistors, are connected between common node 2, which is tied to a first supply voltage Vs (usually the ground Gnd), and respective nodes 3 and 4, hereinafter referred to as charge storage nodes. These nodes 3, 4 are connected to a common node 5 which is tied to a second supply voltage (usually a positive voltage Vc), respectively, through PFETs P1 and P2. Nodes 3 and 4 are also respectively connected to the bit lines BLT and BLC through NFETs N3 and N4, hereinafter referred to as to access transistors. The gate electrodes of NFETs N3 and N4 are connected to the word line WL for READ and WRITE operations.
FIG. 2 is a partial cross-sectional view of the structure of the 6D SRAM cell circuit of FIG. 1 when integrated in a semiconductor substrate according to a conventional CMOS manufacturing process offering stacked polysilicon gate PFET devices (sPFETs). The structure referenced 6 is a good example of the advanced state of the art known to date and is extracted from an article entitled: "A .1 .mu.A stand-by current ground-bounce-immune 1-M bit CMOS SRAM by M. Ando et al, published in the IEEE JSSC vol. 24, N.degree. 6, Dec. 89, pp. 1708-1713. Reference numeral 7 indicates the P type silicon substrate. Numerals 8 indicate the different field recess oxide (ROX) regions that are used to isolate the different active regions of the structure. Numerals 9 are active N+ implanted source and drain regions of the NFETs. Numeral 12 indicates the gate dielectric layer, typically an SiO.sub.2 layer. The highly doped N+ polysilicon gate electrodes of driver NFETs N1 and N2 are respectively referenced 11-1 and 11-2. Polysilicon gate electrode 11-2 forms a buried contact with region 9' which is a protrusion of the drain region 9 of NFET N1. The gate electrodes 11-1 and 11-2 and the source and drain regions of NFETs N1 and N2 are covered by a thin insulating protective layer 12 of SiO.sub.2, which also forms oxide sidewalls or spacers on the lateral sides of gate electrode 11-1 of NFET N1. A polysilicon land 13 surmounts gate electrodes 11-1 and 11-2 and is isolated therefrom by the SiO.sub.2 layer 12. Polysilicon land 13 results from the patterning and selective doping of an intrinsic or lightly doped polysilicon layer that has been deposited to form the body of sPFETs. As apparent from FIG. 2, this polysilicon land 13 is highly doped with a P type dopant except just above gate electrode 11-1. The undoped region forms the channel region of the sPFET Pl while the adjacent P+ doped regions form the source and drain regions thereof. An extension of the drain region of sPFET P1, referred to as the extended drain region, contacts the small portion of gate electrode 11-2, which is exposed through an opening in oxide layer 12. N+ doped gate electrode 11-1 of NFET N1 also serves as the gate electrode of sPFET P1, while layer 12 is the gate dielectric thereof. For each cell, oxide layer 12 is opened in all locations where it is necessary to make a contact between the N+ doped polysilicon gate electrode of a NFET and the adjacent P+ extended drain region of the corresponding sPFET. Note that region 9, protrusion 9', gate electrode 11-2, and the extended drain region of sPFET P1 13 are at the potential of node 3, thereby achieving the desired cross-coupling of the devices as illustrated in the cell circuit of FIG. 1. At this stage of the process, the structure is said to have completed the Master Slice processing steps of a polysilicon gate CMOS FET technology. The structure is consequently passivated by a relatively thick insulating SiO.sub.2 layer 14 of about 500 nm. All of the aforementioned components 7-14 of the structure 6 result from the FEOL (Front End Of the Line) processing.
Elements that will now be described are formed during the personalization steps or BEOL (Back End Of the Line) processing. Numeral 15 is a typical example of a polycide land or line used as a power bus. In FIG. 2, polycide land 15 connects a N+ active region 9 (the source region of a NFET not illustrated in FIG. 2) to Gnd and is hereinafter referred to as the Gnd bus. An additional insulating SiO.sub.2 layer 16 terminates the structure. Layer 16 is provided with contact openings (not shown) to allow appropriate contacting with the metal bit lines BLT and BLC and power busses (e.g. the Vc power bus). As apparent from FIG. 2, all the succeeding layers, and in particular polysilicon layer 13, are conformally deposited, thereby resulting in the typical "corrugated" relief aspect of the upper layers of structure 6.
The cell construction of FIG. 2, wherein PFETs used as load devices are stacked above NFETs, is of great interest in terms of density, because the cell area is only determined by the area of NFETs. However, the disclosed semiconductor structure and its corresponding manufacturing process have some major inconveniences which are recited below.
1. The said conventional manufacturing process is not of the self-aligned type. Self-aligned processes combined with oxide spacers are preferred in order to avoid hot electrons and punch-through problems. In the structure of FIG. 2, no oxide spacers on the sidewalls of gate electrodes are provided to the sPFETs. PA0 2. The structure of FIG. 2 requires six additional masks with respect to a conventional manufacturing process of 6D SRAM cell chips not offering sPFETs. The first mask is used to remove the gate oxide layer 10 above protruded source region 9' of NFET N1 to allow the buried contact between gate electrode 11-2 and said region 9'. The second mask makes an opening above gate electrode 11-2. The third mask delineates the N type lightly doped polysilicon layer 13. The third mask is used to shape the desired polysilicon land wherein sPFET P1 and its related extended drain region (for connection with underlying gate electrode 11-2). The fourth mask is a block-out mask that is required to protect the channel region of sPFET P1 from the implantation of P type dopants, while forming the highly doped P+ source and drain regions thereof, along with said extended drain region. The fifth mask defines contact openings where polycide lands conveying the Gnd potential contact source regions 9 of NFETs e.g. driver transistors. An example of a Gnd bus is shown in FIG. 2. Also, the sixth mask delineates polycide land such as the word lines and some power busses. PA0 3. sPFET P1 is dependent upon the underlying NFET N1 size and lay-out which in turn, results in less flexibility in the design. Because the gate electrode 11-1 of NFET N1 is also the gate electrode of sPFET P1, the layout of the two devices are strongly coupled both in terms of device size and device lay-out. More generally, since the gate length of the NFET (e.g. N1) must be at the minimum allowed by the lithography for maximum performance, so must be the gate length of the corresponding sPFET (e.g. P1). This constitutes a potential source of reliability hazards. For example, if the out-diffusion of the P+ dopants contained in the implanted source and drain regions of the sPFET P1 is not well controlled, the source and drain regions get too large, thereby reducing the effective channel length of sPFET P1. As a consequence, punch-through problems can occur. The channel length of sPFET P1 cannot be increased since this length is dictated by the performance requirements of NFET N1 as mentioned above. In addition, since the block-out mask defining the channel region of sPFET P1 is also at minimum image size, alignment tolerance between this block-out mask and the channel region can result in a channel region not correctly aligned with the gate electrode. PA0 FIGS. 3A and 3B illustrate the effect of misalignment on sPFET P1 as to the introduction of parasitic devices to an ideal PFET P (that would be obtained should misregistration not exist), that has inherently poor performance. In the first case (positive misalignment) shown in FIG. 3A, the diode D (forwardly-biased) and a high value resistor R are in series with the source region s of the ideal PFET P. These parasitic devices decrease the effective gate to source overdrive voltage (VGS- VT) of sPFET P1 (which has already a high threshold voltage VT) and hence will decrease the "ON" current of sPFET P1. In the second case (negative misalignment), shown in FIG. 3B, the parasitic devices: resistor R and diode D (now reversely-biased) are in series with the drain region d of the ideal PFET P and similarly decrease the current capability of sPFET P1. As a result, the latter is far from an ideal PFET P. PA0 4. The gate electrode of the sPFET P1 does not have an optimized work function. Since both NFET N1 and the corresponding sPFET P1 formed thereupon share the same N+ gate electrode 11-1, the gate electrode of the sPFET is therefore of the N+ type while P+ type would have been preferred. It is well recognized that this situation creates punch-through problems, because in this case, the channel region is buried instead of being in surface. Punch-through effects induce leakage currents which are critical for the SRAM cell stand-by power consumption. PA0 5. As pointed out above in conjunction with FIG. 2, the conventional manufacturing process results in a non planarized structure 6. The gate oxide layer 12 and the polysilicon layer 13 forming sPFET P1 are deposited over the castellated topology of the NFET N1 gate electrode 11-1, although slightly smoothed by protective layer 12, thereby creating reliability problems known as "step coverage", since polysilicon layer 13 is much thinner than gate electrode 11-1. PA0 6. A parasitic P+/N+ diode is formed between N+ gate electrode 11-2 of NFET N2 and the P+ extended drain region of sPFET P1. This diode deteriorates the contact quality which is no longer of the ohmic type, thereby slowing down the SRAM cell performance. PA0 7. The word lines WL, some power busses and possibly the local interconnect scheme that makes straps and short distance connections at the silicon wafer level, are made of polycide. Polycide is a quite good conductive material, however it is known to exhibit higher resistivities than metal. PA0 8. Finally, the structure of FIG. 2 has a poor design flexibility because of the difficult contacting of source region of sPFET P1 to Vc power bus because the presence of the polycide lands 15.